반도체 제조라인 레이아웃 평가를 위한 실용적인 Lot 이동거리 계산방법
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영문초록

In this paper, a practical estimation method is developed for the lot travel distance in order to evaluate semiconductor unified fabrication layouts using the absorbing Markov chain. The lot travel distance is defined as the total distance that a lot travels from the first process to the last process; it can be used to investigate whether a fabrication layout design is reasonable. Furthermore, unified fabrication has not yet been introduced in the literature; it is a fabrication method that uses only one type of automated material handling system (AMHS). When designing semiconductor fabrication layouts, every aspect of all alternatives should be investigated meticulously. The widely known and accepted methods, such as sophisticated simulations and mathematical modeling with high accuracy, require an extensive time period to build the model. However, in the early stages of the layout design, simple and insightful methods are required in order to investigate the numerous alternatives during a short time period. This paper presents a simple estimation method for the travel distance of a lot during its lifetime in a fabrication.
  • 가격5,500
  • 페이지수20 페이지
  • 발행년2014
  • 학회명한국생산성학회
  • 저자서민석 ( Min Seok Seo ) , 임대은 ( Dae Eun Lim )
  • 파일형식아크로뱃 뷰어(pdf)
  • 자료번호#3985984
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