목차
[M.Morris MANO] 디지털 논리와 컴퓨터 설계 6장 연습문제
Logic and computer design fundamentals
6단원
2번 8번 14번 20번 26번 32번 38번
Logic and computer design fundamentals
6단원
2번 8번 14번 20번 26번 32번 38번
본문내용
plexer_4to1_arch is begin
process (S, D)
begin
case S is
when "00" => Y <=D(0);
when "01" => Y <=D(1);
when "10" => Y <=D(2);
when "11" => Y <=D(3);
when others => null;
end case;
end process
end multiplexer_4to1_arch;
38. Write a Verilog description for the multiplexer in Figure 4-14 y using a process containing a case statement rather than the continuous assignment statements as shown in Section 4-8.
module aa(S, D, y);
input [1:0] S;
input [3:0] D;
output y;
reg Y;
alwas @(s or D)
begin
case(S)
2'b00 : Y <=D[0];
2'b01 : Y <=D[1];
2'b10 : Y <=D[2];
2'b11 : Y <=D[3];
endcase;
end
endmodule
process (S, D)
begin
case S is
when "00" => Y <=D(0);
when "01" => Y <=D(1);
when "10" => Y <=D(2);
when "11" => Y <=D(3);
when others => null;
end case;
end process
end multiplexer_4to1_arch;
38. Write a Verilog description for the multiplexer in Figure 4-14 y using a process containing a case statement rather than the continuous assignment statements as shown in Section 4-8.
module aa(S, D, y);
input [1:0] S;
input [3:0] D;
output y;
reg Y;
alwas @(s or D)
begin
case(S)
2'b00 : Y <=D[0];
2'b01 : Y <=D[1];
2'b10 : Y <=D[2];
2'b11 : Y <=D[3];
endcase;
end
endmodule
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