VHDL 프로그램 정리

소개글

VHDL 프로그램 정리에 대한 보고서 자료입니다.

본문내용

);
elsif (rising_edge(clk)) then
if (qout=511) then
qout <= (others => '0');
else
qout <= qout + 1;
end if;
end if;
end process;
end behav;
■ D F/F(16비트)
library ieee;
use ieee.std_logic_1164.all;
entity dffp16 is
port(clk, rst : in std_logic;
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0));
end dffp16;
architecture behav of dffp16 is
begin
process(clk, rst)
begin
if (rst='0') then
dout <= (others => '0');
elsif (falling_edge(clk)) then
dout <= din;
end if;
end process;
end behav;
■ N-bit Latch
library ieee;
use ieee.std_logic_1164.all;
entity ih_n is
generic(size : integer := 4);
port(rst, en : in std_logic;
din : in std_logic_vector(size-1 downto 0);
q : out std_logic_vector(size-1 downto 0));
end ih_n;
architecture behav of ih_n is
begin
process(rst, en, din)
begin
if (rst='0') then
q <= (others => '0');
elsif (en='1') then
q <= din;
end if;
end process;
end behav;
■ Mod-64 Counter(Ripple carry)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt64e is
port(clk, ld, en : in std_logic;
rst : in std_logic;
rco : out std_logic;
q : out std_logic_vector(5 downto 0));
end cnt64e;
architecture behav of cnt64e is
signal qout : std_logic_vector(5 downto 0);
begin
q <= qout;
process(clk, rst)
begin
if (rst='0') then
qout <= (others => '0');
rco <= '0';
elsif (rising_edge(clk)) then
if (ld='1') then
qout <= (others => '0');
rco <= '0';
elsif (en='1') then
if (qout=63) then
qout <= (others => '0');
rco <= '1';
else
qout <= qout + 1;
rco <= '0';
end if;
end if;
end if;
end process;
end behav;
■ Mod-16 Down Counter(Ripple carry)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity d_cnt16 is
port(clk, ld, dn : in std_logic;
rst : in std_logic;
pin : in std_logic_vector(3 downto 0);
rco : out std_logic;
q : out std_logic_vector(3 downto 0));
end d_cnt16;
architecture behav of d_cnt16 is
signal qout : std_logic_vector(3 downto 0);
begin
q <= qout;
process(clk, rst)
begin
if (rst='0') then
qout <= (others => '0');
rco <= '0';
elsif (rising_edge(clk)) then
if (ld='1') then
qout <= pin;
if (pin=0) then
rco <= '1';
end if;
elsif (dn='1') then
if (qout=1) then
qout <= (others => '0');
rco <= '1';
else
qout <= qout - 1;
rco <= '0';
end if;
end if;
end if;
end process;
end behav;
[교재내용]
■ 1비트 Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a, b, cin : in std_logic;
sum, cout : out std_logic);
end full_adder;
architecture behav of full_adder is
begin
process(a, b, cin)
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end process;
end behav;
■ 1비트 Full Subtracter
library ieee;
use ieee.std_logic_1164.all;
entity full_sub is
port(a, b, bi : in std_logic;
di, bo : out std_logic);
end full_sub;
architecture behav of full_sub is
begin
process (a, b, bi)
begin
di <= a xor b xor bi;
bo <= ((not a) and b) or ((not a) and bi) or (b and bi);
end process;
end behav;
[실험7] => 순차회로
■ Decoder 4 to 16
■ Ring Counter

키워드

VHDL,   디지털,   프로그램,   코드