32bitMIPS Verilog Source Code (MultiCycle)

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32bitMIPS Verilog Source Code (MultiCycle)에 대한 보고서 자료입니다.

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본문내용

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: 32bit MultiCycle MIPS - Top module -
// Project Name: 32bit MultiCycle MIPS
//////////////////////////////////////////////////////////////////////////////////
module MultiCycle_MIPS(clk, rst, MemData, MemRead, MemWrite, Address, MWritedata, c_PC,
c_Instruction, c_MDR);

input clk, rst;

input [31:0] MemData;
output [31:0] c_PC;
output [31:0] c_Instruction;
output [31:0] c_MDR;
output MemRead;
output MemWrite;
output [31:0] Address;
output [31:0] MWritedata;

// Main Control Unit wire
wire PCWriteCond;
wire PCWrite;
wire IorD;
wire MemRead;
wire MemWrite;
wire MemtoReg;
wire IRWrite;
wire CauseWrite;
wire IntCause;
wire EPCWrite;
wire [1:0]PCSource;
wire [1:0]ALUOp;
wire [1:0]ALUSrcB;
wire ALUSrcA;
wire RegWrite;
wire RegDst;

//ALU Control Unit wire
wire [2:0]ALU_Op;

//ALU wire
wire [31:0]ALU_Result;
wire [31:0]ALU_a;
wire [31:0]ALU_b;
wire Overflow;
wire Zero;

//Registers wire
wire [4:0]Writeregister;
wire [31:0]Writedata;
wire [31:0]Readdata1;
wire [31:0]Readdata2;

//Program Counter wire
wire [31:0]PCIn;
wire [31:0]PC;
wire PCctrl;
wire PCWriteCond2;

assign PCWriteCond2 = Zero && PCWriteCond;
assign PCctrl = PCWriteCond2 || PCWrite;

//Instruction Register wire
wire [31:0]Instruction;

//ShiftLeft 2 wire
wire [31:0]ShiftLeft2_1;
wire [27:0]ShiftLeft2_2;
wire [31:0]JumpAddr;

//ALUOut Register wire
wire [31:0]ALUOut;

키워드

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