VHDL 프로그램 정리

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VHDL 프로그램 정리에 대한 보고서 자료입니다.

본문내용

nd if;
end case;
end process;
end behav;
■ 1비트 Full Adder 직렬 가산기
library ieee;
use ieee.std_logic_1164.all;
entity SAdd is
generic(width : integer := 8);
port(clk, rst : in std_logic;
cin : in std_logic;
a, b : in std_logic_vector(width-1 downto 0);
cout : out std_logic;
done : out std_logic;
sum : out std_logic_vector(width-1 downto 0));
end SAdd;
architecture struct of SAdd is
component sa_con
port(clk, rst, z : in std_logic;
done, cout, sh : out std_logic);
end component;
component sa_dp
generic(width : integer := 8);
port(clk, rst : in std_logic;
cin : in std_logic;
a, b : in std_logic_vector(width-1 downto 0);
sh : in std_logic;
zout : out std_logic;
sum : out std_logic_vector(width-1 downto 0));
end component;
signal sh, zout : std_logic;
begin
C1: sa_con port map(clk=>clk, rst=>rst, z=>zout, done=>done, cout=>cout, sh=>sh);
D1: sa_dp port map(clk=>clk, rst=>rst, cin=>cin, a=>a, b=>b, sh=>sh, zout=>zout, sum=>sum);
end struct;
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sa_dp is
generic(width : integer := 8);
port(clk, rst : in std_logic;
cin : in std_logic;
a, b : in std_logic_vector(width-1 downto 0);
sh : in std_logic;
zout : out std_logic;
sum : out std_logic_vector(width-1 downto 0));
end sa_dp;
architecture behav of sa_dp is
signal x, y, ts : std_logic_vector(width-1 downto 0);
signal s1, zin, z : std_logic;
begin
-- 1 bit FA --
process(x(0), y(0), z)
begin
s1 <= x(0) xor y(0) xor z;
zin <= (x(0) and y(0)) or (x(0) and z) or (y(0) and z);
end process;
-- carry store --
process(clk, rst)
begin
if (rst='1') then
z <= cin;
elsif (clk'event and clk='1') then
z <= zin;
end if;
end process;
-- output --
sum <= ts;
zout <= z;
-- shift register --
process(clk, rst)
begin
if (rst='1') then
x <= a;
y <= b;
ts <= (others => '0');
elsif (clk'event and clk='1') then
if (sh='1') then
x <= '0' & x(width-1 downto 1);
y <= '0' & y(width-1 downto 1);
ts <= s1 & ts(width-1 downto 1);
end if;
end if;
end process;
end behav;
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sa_con is
port(clk, rst, z : in std_logic;
done, cout, sh : out std_logic);
end sa_con;
architecture behav of sa_con is
signal ps, ns : integer range 0 to 9;
begin
-- state register --
process(clk, rst)
begin
if (rst='1') then
ps <= 0;
elsif (clk'event and clk='1') then
ps <= ns;
end if;
end process;
-- state transition --
process(rst, ps)
begin
done <= '0'; sh<= '0'; cout<= '0';
case ps is
when 0 =>
if (rst='0') then
ns <= 1;
else
ns <= 0;
end if;
when 1 =>
ns <= 2; sh <= '1';
when 2 =>
ns <= 3; sh <= '1';
when 3 =>
ns <= 4; sh <= '1';
when 4 =>
ns <= 5; sh <= '1';
when 5 =>
ns <= 6; sh <= '1';
when 6 =>
ns <= 7; sh <= '1';
when 7 =>
ns <= 8; sh <= '1';
when 8 =>
ns <= 9; sh <= '1';
when 9 =>
if (rst='1') then
ns <= 0;
else
ns <= 9;
end if;
end case;
end process;
end behav;

키워드

VHDL,   디지털,   프로그램,   코드