카운터설계 (VHDL)

본문내용

ieee;
use ieee.std_logic_1164.all;
entity keyinh is
port( data, noclk : in std_logic;
y_out : buffer std_logic );
end keyinh;
architecture sample of keyinh is
signal data1 : std_logic;
--signal noclk : std_logic;
begin
process(noclk)
begin
if (noclk'event and noclk = '1') then
data1 <= data;
if (data1='0') and (data='1') then
y_out <= '1';
else
y_out <= '0';
end if;
end if;
end process;
end sample;
< 시뮬레이션 - Timing >
< 시뮬레이션 - Functional >
과제5.
앞서 설명한 moore machine을 3개의 process로 표현한 VHDL 문장은 다음과 같으며 이를 수행하고 그 결과를 분석하라.
Source Code
library ieee;
use ieee.std_logic_1164.all;
entity moore_3p is
port( clk, x, reset: in std_logic;
y: out std_logic_vector(2 downto 0) );
end moore_3p;
architecture sample of moore_3p is
type states is (s0, s1, s2, s3);
signal present_state, next_state : states;
begin
p1 : process(present_state, x)
begin
case present_state is
when s0 =>
if x='1' then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
if x='0' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
if x='1' then
next_state <= s3;
else
next_state <= s2;
end if;
when s3 =>
if x='0' then
next_state <= s0;
else
next_state <= s3;
end if;
end case;
end process;
p2 : process(reset, clk) -- Register Operation
begin
if reset='1' then
present_state <= s0;
elsif clk'event and clk='1' then
present_state <= next_state;
end if;
end process;
p3 : process(present_state)
begin
case present_state is
when s0 =>
y <= "000";
when s1 =>
y <= "001";
when s2 =>
y <= "011";
when s3 =>
y <= "111";
end case;
end process;
end sample;
< 시뮬레이션 - Timing >
< 시뮬레이션 - Functional >
과제6.
다음의 entity Mealy_3p의 architectureans p1,p2 및 p3는 앞서 설명한 세 개의 process로 기술한 것이다. 아래의 entity Mealy_3p를 수행하고 그 결과를 분석하라.
Source Code
library ieee;
use ieee.std_logic_1164.all;
entity mealy_3p is
port( clk, x, reset : in std_logic;
y : out std_logic_vector(2 downto 0) );
end mealy_3p;
architecture sample of mealy_3p is
type states is (s0, s1, s2, s3);
signal present_state, next_state : states;
begin
p1 : process(present_state, x)
begin
case present_state is
when s0 =>
if x='1' then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
if x='0' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
if x='1' then
next_state <= s3;
else
next_state <= s2;
end if;
when s3 =>
if x='0' then
next_state <= s0;
else
next_state <= s3;
end if;
end case;
end process;
p2 : process(reset, clk) -- present state -clk-> next state : Register Operation
begin
if reset='1' then
present_state <= s0;
elsif clk'event and clk='1' then
present_state <= next_state;
end if;
end process;
p3 : process(present_state, x) --print
begin
case present_state is
when s0 =>
if x = '1' then
y <= "000";
else
y <= "111";
end if;
when s1 =>
if x = '1' then
y <= "000";
else
y <= "001";
end if;
when s2 =>
if x = '1' then
y <= "011";
else
y <= "001";
end if;
when s3 =>
if x = '1' then
y <= "011";
else
y <= "111";
end if;
end case;
end process;
end sample;
< 시뮬레이션 >

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