[VHDL]8point IFFT/FFT 구현

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[VHDL]8point IFFT/FFT 구현에 대한 보고서 자료입니다.

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T-1 DOWNTO 0);
yi_out => dlyi0_out, --: OUT SIGNED(N_BIT-1 DOWNTO 0);
yq_out => dlyq0_out); --: OUT SIGNED(N_BIT-1 DOWNTO 0));
UCMUL_0: cmul
GENERIC MAP(N_BIT+1, 10, N_BIT+1)
PORT MAP(xi => cmuli0_in, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
xq => cmulq0_in, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
wi => wi0, --: IN SIGNED(N_BIT2-1 DOWNTO 0);
wq => wq0, --: IN SIGNED(N_BIT2-1 DOWNTO 0);
yi => cmuli0_out, --: OUT SIGNED(N_BIT3-1 DOWNTO 0);
yq => cmulq0_out); --: OUT SIGNED(N_BIT3-1 DOWNTO 0));
UEXPLUT_0: explut0
PORT MAP(ifft_mode => ifft_mode, --: IN STD_LOGIC;
sel => cnt, --: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cos_out => wi0, --: OUT SIGNED(9 DOWNTO 0);
sin_out => wq0); --: OUT SIGNED(9 DOWNTO 0));
-- 2nd Stage --
UBF2_1: bf2sdf GENERIC MAP(N_BIT+1)
PORT MAP(sel => cnt(1), --: IN STD_LOGIC;
xi0 => dlyi1_out, --: IN SIGNED(N_BIT1 DOWNTO 0);
xq0 => dlyq1_out, --: IN SIGNED(N_BIT1 DOWNTO 0);
xi1 => cmuli0_out, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
xq1 => cmulq0_out, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
yi0 => cmuli1_in, --: OUT SIGNED(N_BIT1 DOWNTO 0);
yq0 => cmulq1_in, --: OUT SIGNED(N_BIT1 DOWNTO 0);
yi1 => dlyi1_in, --: OUT SIGNED(N_BIT1 DOWNTO 0);
yq1 => dlyq1_in); --: OUT SIGNED(N_BIT1 DOWNTO 0));
UDLY_1: delay GENERIC MAP(2, N_BIT+2)
PORT MAP(rstn => rstn, --: IN STD_LOGIC;
clk => clk, --: IN STD_LOGIC;
xi_in => dlyi1_in, --: IN SIGNED(N_BIT-1 DOWNTO 0);
xq_in => dlyq1_in, --: IN SIGNED(N_BIT-1 DOWNTO 0);
yi_out => dlyi1_out, --: OUT SIGNED(N_BIT-1 DOWNTO 0);
yq_out => dlyq1_out); --: OUT SIGNED(N_BIT-1 DOWNTO 0));
UCMUL_1: cmul
GENERIC MAP(N_BIT+2, 10, N_BIT+2)
PORT MAP(xi => cmuli1_in, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
xq => cmulq1_in, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
wi => wi1, --: IN SIGNED(N_BIT2-1 DOWNTO 0);
wq => wq1, --: IN SIGNED(N_BIT2-1 DOWNTO 0);
yi => cmuli1_out, --: OUT SIGNED(N_BIT3-1 DOWNTO 0);
yq => cmulq1_out); --: OUT SIGNED(N_BIT3-1 DOWNTO 0));
UEXPLUT_1: explut1
PORT MAP(ifft_mode => ifft_mode, --: IN STD_LOGIC;
sel => cnt(1 DOWNTO 0), --: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cos_out => wi1, --: OUT SIGNED(9 DOWNTO 0);
sin_out => wq1); --: OUT SIGNED(9 DOWNTO 0));
-- 3nd Stage --
UBF2_2: bf2sdf GENERIC MAP(N_BIT+2)
PORT MAP(sel => cnt(0), --: IN STD_LOGIC;
xi0 => dlyi2_out, --: IN SIGNED(N_BIT1 DOWNTO 0);
xq0 => dlyq2_out, --: IN SIGNED(N_BIT1 DOWNTO 0);
xi1 => cmuli1_out, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
xq1 => cmulq1_out, --: IN SIGNED(N_BIT1-1 DOWNTO 0);
yi0 => yi, --: OUT SIGNED(N_BIT1 DOWNTO 0);
yq0 => yq, --: OUT SIGNED(N_BIT1 DOWNTO 0);
yi1 => dlyi2_in, --: OUT SIGNED(N_BIT1 DOWNTO 0);
yq1 => dlyq2_in); --: OUT SIGNED(N_BIT1 DOWNTO 0));
UDLY_2: delay GENERIC MAP(1, N_BIT+3)
PORT MAP(rstn => rstn, --: IN STD_LOGIC;
clk => clk, --: IN STD_LOGIC;
xi_in => dlyi2_in, --: IN SIGNED(N_BIT-1 DOWNTO 0);
xq_in => dlyq2_in, --: IN SIGNED(N_BIT-1 DOWNTO 0);
yi_out => dlyi2_out, --: OUT SIGNED(N_BIT-1 DOWNTO 0);
yq_out => dlyq2_out); --: OUT SIGNED(N_BIT-1 DOWNTO 0));
END;
--========================= End of 2pdft ================================--

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VHDL,   DSP,   FFT,   IFFT,   통신