[공학기술]vhdl-D flipflop, 8bit register

소개글

[공학기술]vhdl-D flipflop, 8bit register에 대한 보고서 자료입니다.

본문내용

0000000\";
end if;
end process;
end behave;
테스트 벤치 코드
library ieee;
use ieee.std_logic_1164.all;
entity tb_resister is
end tb_resister;
architecture behave of tb_resister is
signal rst:std_logic;
signal clk:std_logic:=\'0\';
signal d,q:std_logic_vector(7 downto 0);
component resister
port(rst,clk:in std_logic;
d:in std_logic_vector;
q:out std_logic_vector);
end component;
begin
T1 : resister
port map(rst,clk,d,q);
rst<=\'0\', \'1\' after 30 ns;
clk<= not clk after 20 ns;
d<=\"00000000\", \"11111111\" after 10 ns, \"00010001\" after 70 ns, \"10011010\" after 130 ns,
\"01100101\" after 190 ns;
end behave;
결과 파형

키워드

vhdl,   플립플랍,   레지스터,   flip flop,   register