구조적 모델링

소개글

구조적 모델링에 대한 보고서 자료입니다.

본문내용

begin
u0:f_addr
port map(x, y, c_in, s_out, c_out);
x <= \'0\', \'1\' after 400 ns;
y <= \'0\', \'1\' after 200 ns, \'0\' after 400 ns, \'1\' after 600 ns;
c_in <= \'0\', \'1\' after 100 ns, \'0\' after 200 ns, \'1\' after 300 ns
, \'0\' after 400 ns, \'1\' after 500 ns, \'0\' after 600 ns, \'1\' after 700 ns;
end tb_behave;
구조적 모델링 파형
동작적 모델링
Full Adder
Library IEEE;
use IEEE.std_logic_1164.all;
entity f_addr_bh is
port(
x, y, c_in : in std_logic;
s_out, c_out : out std_logic
);
end f_addr_bh;
architecture be_f_addr_bh of f_addr_bh is
begin
process(x, y, c_in)
begin
if c_in=\'0\' then
if x=\'1\' and y=\'1\' then
c_out <= \'1\';
else c_out <=\'0\';
end if;
if x=y then
s_out <= \'0\';
else s_out <= \'1\';
end if;
else
if x=\'0\' and y=\'0\' then
c_out <= \'0\';
else c_out <= \'1\';
end if;
if x=y then
s_out <= \'1\';
else s_out <= \'0\';
end if;
end if;
end process;
end be_f_addr_bh;
Full Adder Test Bench
Library IEEE;
use IEEE.std_logic_1164.all;
entity tb_f_addr_bh is
end tb_f_addr_bh;
architecture tb_behave of tb_f_addr_bh is
signal x, y, c_in : std_logic;
signal c_out, s_out : std_logic;
component f_addr_bh
port(
x, y, c_in : in std_logic;
s_out, c_out : out std_logic
);
end component;
begin
u0: f_addr_bh
port map(x=>x, y=>y, c_in=>c_in, c_out=>c_out, s_out=>s_out);
x <= \'0\', \'1\' after 400 ns;
y <= \'0\', \'1\' after 200 ns, \'0\' after 400 ns, \'1\' after 600 ns;
c_in <= \'0\', \'1\' after 100 ns, \'0\' after 200 ns, \'1\' after 300 ns
, \'0\' after 400 ns, \'1\' after 500 ns, \'0\' after 600 ns, \'1\' after 700 ns;
end tb_behave;
동작적 모델링 파형

키워드

구조적 모델링,   모델링,   공학,   설계