vhdl_시계

본문내용

op_s:std_logic;
SIGNALclear_s:std_logic;
SIGNALth_s:integer;
SIGNALtm_s:integer;
SIGNALts_s:integer;
SIGNALwm_s:integer;
SIGNALws_s:integer;
SIGNALwms_s:integer;
--clk_gen----------------------------------------------------
COMPONENT clk_gen
PORT(
clk5M: INSTD_LOGIC;
reset: INSTD_LOGIC;
clk500: OUTSTD_LOGIC);
END COMPONENT;
-------------------------------------------------------------
--mode_set---------------------------------------------------
COMPONENT mode_set
PORT(
clk500: INSTD_LOGIC;
reset: INSTD_LOGIC;
mode_in: INSTD_LOGIC;
time_set_in: INSTD_LOGIC;
clear_in: INSTD_LOGIC;
start_stop_in: INSTD_LOGIC;
mode_out: OUTSTD_LOGIC;
time_set: OUTSTD_LOGIC;
start_stop: OUTSTD_LOGIC;
clear: OUTSTD_LOGIC);
END COMPONENT;
-------------------------------------------------------------
--time-------------------------------------------------------
COMPONENT time
PORT(
clk500: INSTD_LOGIC;
reset: INSTD_LOGIC;
mode_time: INSTD_LOGIC;
time_set_time: INSTD_LOGIC;
start_stop_time: INSTD_LOGIC;
clear_time: INSTD_LOGIC;
Tmin: OUTINTEGER range 0 to 60;
Tsec: OUTINTEGER range 0 to 60;
Thour: OUTINTEGER range 0 to 24);
END COMPONENT;
-------------------------------------------------------------
--stop_watch-------------------------------------------------
COMPONENT stop_watch
PORT(
clk500: INSTD_LOGIC;
reset: INSTD_LOGIC;
mode_stop: INSTD_LOGIC;
st_stop: INSTD_LOGIC;
clear_stop: INSTD_LOGIC;
wmin: OUTINTEGER RANGE 0 to 60;
wsec: OUTINTEGER RANGE 0 to 60;
wmsec: OUTINTEGER RANGE 0 to 100);
END COMPONENT;
-------------------------------------------------------------
--segment----------------------------------------------------
COMPONENT segment
PORT(
clk500: INSTD_LOGIC;
reset: INSTD_LOGIC;
hour_seg: ININTEGER RANGE 0 to 24;
min_seg: ININTEGER RANGE 0 to 60;
sec_seg: ININTEGER RANGE 0 to 60;
wms_seg: ININTEGER RANGE 0 to 100;
ws_seg: ININTEGER RANGE 0 to 60;
wm_seg: ININTEGER RANGE 0 to 60;
time_set_seg: INSTD_LOGIC;
mode_seg: INSTD_LOGIC;
number: OUTSTD_LOGIC_VECTOR(6 downto 0);
encode: OUTSTD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
-------------------------------------------------------------
BEGIN
u1 : clk_gen
PORT MAP(
clk5M,
reset,
clk500);
u2 : mode_set
PORT MAP(
clk500,
reset,
mode_in => mode_in_main,
time_set_in => time_set_main,
clear_in => clear_main,
start_stop_in => start_stop_main,
mode_out => mode_s,
time_set => time_set_s,
start_stop => start_stop_s,
clear => clear_s);
u3 : time
PORT MAP(
clk500,
reset,
mode_time => mode_s,
time_set_time => time_set_s,
start_stop_time => start_stop_s,
clear_time => clear_s,
Tmin => tm_s,
Tsec => ts_s,
Thour => th_s);
u4 : stop_watch
PORT MAP(
clk500,
reset,
mode_stop => mode_s,
st_stop => start_stop_s,
clear_stop => clear_s,
wmin => wm_s,
wsec => ws_s,
wmsec => wms_s);
u5 : segment
PORT MAP(
clk500,
reset,
hour_seg => th_s,
min_seg => tm_s,
sec_seg => ts_s,
wms_seg => wms_s,
ws_seg => ws_s,
wm_seg => wm_s,
time_set_seg => time_set_s,
mode_seg => mode_s,
number => number_main,
encode => encoder_main);
END time_main;

키워드

vhdl_시계,   Healthcare Embedded System,   시계