논리게이트 - VHDL 설계 언어 실습

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논리게이트 - VHDL 설계 언어 실습에 대한 보고서 자료입니다.

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본문내용

ture data_flow of comp is
begin
equal <= not(a(3) xor b(3) )
and not( a(2) xor b(2) )
and not( a(1) xor b(1) )
and not( a(0) xor b(0) );
end data_flow;
2.시뮬레이션
1)flow summary
2) wave form
3) time analyzer Summary
3. 블록다이어그램
◆ comp2(process문 사용)
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity comp2 is
port (a, b : in bit_vector (3 downto 0);
equal : out bit);
end comp2;
architecture sample of comp2 is
begin
process (a,b)
begin
if a = b then
equal <= '1';
else
equal <= '0';
end if;
end process;
end sample;
2.시뮬레이션
1) flow summary
2) waveform
3) time analysis summary
3. 블록 다이어그램
◆ system
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity system is
port(k1,k2,k3 : in bit;
y_out : out bit);
end system;
architecture sample of system is
sgnal cn : bit ;
begin
cn <= k1 nand k2;
y_out <= cn xor k3;
end sample;
2. 시뮬레이션
1) Flow summary
2) Waveform
3) time analyzer Summary
3. 블록다이어그램
1) 게이트
2) 블록
◆ sys_var
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity sys_var is
port (a, b, c : in bit;
y_out : out bit);
end sys_var;
architecture sample of sys_var is
begin
process (a, b, c)
variable temp : bit;
begin
temp :='1';
temp :=a and temp;
temp :=b and temp;
temp :=c and temp;
y_out <= temp;
end process;
end sample;
2. 시뮬레이션
1) Flow summary
2) Waveform
3) time analyzer Summary
3. 블록다이어그램
1) 블록
2) 게이트
◆ xor_inv
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity xor_inv is
port (x : in bit; y : out bit);
end xor_inv;
architecture sample of xor_inv is
constant sel : bit :='1';
begin
y <= x xor sel;
end sample;
2.시뮬레이션
1)flow summary
2) wave form
3) time analyzer Summary
3. 블록다이어그램
1)블록
2)게이트
◆ 구조적표현
1. 소스
library ieee;
use ieee.std_logic_1164.all;
entity compo is
port( a,b : in bit_vector(1 downto 0);
y : out bit);
end compo;
architecture comp_structure of compo is
signal x : bit_vector (1 downto 0);
component xnor2
port(in1, in2 : in bit;
y : out bit);
end component;
component and_2
port(in1, in2 : in bit;
y : out bit);
end component;
begin
V1 : xnor2
port map (a(1), b(1), x(1));
V2 : xnor2
port map (a(0), b(0), x(0));
V3 : and_2
port map (x(0), x(1), y);
end comp_structure;
※ library 추가
→ →
2. 시뮬레이션 결과
1) flow summary
2) waveform
3) time analyzer summary
3. 블록다이어그램
1)게이트
2)블록
◆ logic_sp
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity logic_sp is
port ( a,b : in bit_vector(3 downto 0);
c : out bit_vector(3 downto 0);
w,x,y,k,l,m : in std_logic;
z,n : out std_logic);
end logic_sp;
architecture test of logic_sp is
Signal cn : bit;
begin
c <= a or b ;
z <= (w and x) and y ;
n <= (k nor l) xor m ;
end test;
2.시뮬레이션
1.flow summary
2) waveform
3) time analysis summary
3. 블록다이어그램
1) 게이트
2) 블록
◆ logic
1. 소스
library ieee;
use ieee.std_logic_1164.all;
entity logic is
port(a,b,c :in bit;
y :out bit);
end logic;
architecture sample of logic is
signal w, x : bit;
begin
process (a,b,c)
begin
w <= a or b;
x <= b nand c;
y <= w xor x;
end process;
end sample;
2. 시뮬레이션
1) flow summary
2) wave form
3) time analyzer summary
3. 블록 다이어그램
1) 게이트
2) 블록

키워드

논리게이트,   VHDL 설계 ,   언어 실습