[논리회로설계] vhdl을 이용한 도어락(door lock) 설계

소개글

[논리회로설계] vhdl을 이용한 도어락(door lock) 설계에 대한 보고서 자료입니다.

목차

1. 도어락의 개요
2. 입력, 출력 및 상태
3. 동작원리
4. 다이어그램
5 소스 코드
6. Test Banch 코드
7. 시뮬레이션 결과

본문내용

f door_lock_mod_tb is
component door_lock
port ( clk : in std_logic;
rst : in std_logic;
ps_start : in std_logic;
ps_end : in std_logic;
ps_mod : in std_logic;
ps_num : in std_logic_vector (3 downto 0);
door_open : out std_logic;
alarm : out std_logic );
end component;
signal clk : std_logic;
signal rst : std_logic;
signal ps_start : std_logic;
signal ps_end : std_logic;
signal ps_mod : std_logic;
signal ps_num : std_logic_vector (3 downto 0);
signal door_open : std_logic;
signal alarm : std_logic;
begin
uut : door_lock port map(clk, rst, ps_start,ps_end,ps_mod,ps_num,door_open);
tb_rst : process
begin
rst <='1'; wait;
end process;
tb_mod : process
begin
ps_mod <='0'; wait for 5 ns;
ps_mod <='1'; wait for 10 ns;
ps_mod <='0'; wait;
end process;
tb_clk : process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
tb_ps_end : process
begin
ps_end <= '0'; wait for 25 ns;
ps_end <= '1'; wait for 10 ns;
ps_end <= '0'; wait for 50 ns;
ps_end <= '1'; wait for 10 ns;
ps_end <= '0'; wait;
end process;
tb_ps_num : process
begin
ps_num <="0000"; wait for 10 ns;
ps_num <="1101"; wait for 60 ns;
ps_num <="1001"; wait;
end process;
end;
③ 알람 확인
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity door_lock_alarm_tb is
end door_lock_alarm_tb;
architecture door_lock of door_lock_alarm_tb is
component door_lock
port ( clk : in std_logic;
rst : in std_logic;
ps_start : in std_logic;
ps_end : in std_logic;
ps_mod : in std_logic;
ps_num : in std_logic_vector (3 downto 0);
door_open : out std_logic;
alarm : out std_logic );
end component;
signal clk : std_logic;
signal rst : std_logic;
signal ps_start : std_logic;
signal ps_end : std_logic;
signal ps_mod : std_logic;
signal ps_num : std_logic_vector (3 downto 0);
signal door_open : std_logic;
signal alarm : std_logic;
begin
uut : door_lock port map(clk, rst, ps_start,ps_end,ps_mod,ps_num,door_open);
tb_rst : process
begin
-- rst <= '0'; wait for 5 ns;
rst <='1'; wait;
end process;
tb_clk : process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
tb_ps_start : process
begin
ps_start <='0'; wait for 5 ns;
ps_start <='1'; wait for 10 ns;
ps_start <='0'; wait for 70 ns;
ps_start <='1'; wait for 10 ns;
ps_start <='0'; wait for 70 ns;
ps_start <='1'; wait for 10 ns;
ps_start <='0'; wait for 70 ns;
ps_start <='1'; wait for 10 ns;
ps_start <='0'; wait;
end process;
tb_ps_end : process
begin
ps_end <= '0'; wait for 25 ns;
ps_end <= '1'; wait for 10 ns;
ps_end <= '0'; wait for 70 ns;
ps_end <= '1'; wait for 10 ns;
ps_end <= '0'; wait for 70 ns;
ps_end <= '1'; wait for 10 ns;
ps_end <= '0'; wait for 70 ns;
ps_end <= '1'; wait for 10 ns;
ps_end <= '0'; wait;
end process;
tb_ps_num : process
begin
ps_num <="0000"; wait for 15 ns;
ps_num <="1001"; wait for 80 ns;
ps_num <="1111"; wait for 80 ns;
ps_num <="1110"; wait for 80 ns;
ps_num <="1101"; wait;
end process;
end;
7. 시뮬레이션 결과
① 입력모드 확인
② 수정모드 확인
③ 알람 확인 1
④ 알람 확인 2

키워드

논리회로설계,   vhdl,   도어락,   door lock,   도어락 설계,   소스 코드,   시뮬레이션 결과