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y IS
PORT( Clock:INSTD_LOGIC;
w :INSTD_LOGIC;
Resetn:INSTD_LOGIC;
z : OUTSTD_LOGIC);
END mealy;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS(A,B,C,D);
SIGNAL y: State_type;
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
y <= A;
ELSIF(Clock'EVENT AND Clock ='1') THEN
CASE y IS
WHE
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