32bit MIPS Processor 설계 Verilog (레포트)

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32bit MIPS Processor 설계 Verilog (레포트)에 대한 보고서 자료입니다.

목차

1. 개 요 ...................................................................................................................................................................................................................................... 3
1) 프로젝트 목표 .......................................................................................................................................................................................................................................................................................................................................................... 3
2) Instruction ................................................................................................................................................................................................................................................................................................................................................................. 3
2. ANDI, ORI 구현 .................................................................................................................................................................................................................... 5
1) Instruction Code 분석 ......................................................................................................................................................................................................................................................................................................................................... 5
2) Instruction 특징 분석 .......................................................................................................................................................................................................................................................................................................................................... 5
3) 각 특징에 따른 세부 구현 계획 ..................................................................................................................................................................................................................................................................................................................... 5
4) 모듈 수정 및 최종 구현 ..................................................................................................................................................................................................................................................................................................................................... 6
5) 블록도 수정 부분 확인 ........................................................................................................................................................................................................................................................................................................................................ 7
3. 서브 모듈 .............................................................................................................................................................................................................................. 8
1) Main Control Unit ................................................................................................................................................................................................................................................................................................................................................. 8
2) ALU Control Unit ................................................................................................................................................................................................................................................................................................................................................... 9
3) ALU ......................................

본문내용

1. 개 요 1) 프로젝트 목표 - R-type, LW, SW, BEQ,, J, ANDI, ORI 명령어를 수행 할 수 있는 32bit MIPS 설계 ※ R-type의 경우 add와 sub를 구현

2) Instruction - 구현해야 하는 Instruction은 총 7종류로 구성된다. ① R-type : 000000의 Op Code를 가지며, 최하위 6bit인 Function 필드 값으로 명령이 선택된다. - ADD ( Addition )

→ 레지스터 번호가 rs와 rt인 두 레지스터에 저장된 값을 더해 번호가 rd인 레지스터에 쓴다. ( Reg[rd] ← Reg[rs] + Reg[rt] )

- SUB ( Subtraction )

→ 레지스터번호 rs에 저장된 값에서 레지스터번호 rt에 저장된 값을 빼서 레지스터번호 rd에 저장한다. ( Reg[rd] ← Reg[rs] - Reg[rt] )

② LW ( Load Word )

→ 레지스터번호 base에 있는 값과 offset값을 더해서 나온 값을 주소로 하는 메모리에 저장된 값을 레지스터 번 호 rt의 레지스터에 쓴다. ( Reg[rt] ← Memory[Reg[base] + offset] )

키워드

MIPS,   Verilog,   디지털시스템,   밉스,   베리로그,   베릴로그,   멀티사이클