목차
1. 컴퓨터에 대한 제어 함수와 마이크로 연산
2 . 레지스터와 메모리에 대한 제어
2.1 Statements and circuits associated with AR
2.2 Statements and circuits associated with PC
2.3 Statements and circuits associated with DR
2.4 Statements and circuits associated with AC
2.5 Statements and circuits associated with IR
2.6 Statements and circuits associated with TR
2.7 Statements and circuits associated with OUTR
2.8 Statements and circuits associated with INPR
2.9 Statements and circuits associated with SC
3. 단일 플립플롭에 대한 제어
3.1 Statements and circuits associated with I
3.2 Statements and circuits associated with S
3.3 Statements and circuits associated with E
3.4 Statements and circuits associated with R
3.5 Statements and circuits associated with IEN
3.6 Statements and circuits associated with FGI
3.7 Statements and circuits associated with FGO
4. 메모리에 대한 제어
5 공통 버스에 대한 제어
6. 누산기 논리의 설계
2 . 레지스터와 메모리에 대한 제어
2.1 Statements and circuits associated with AR
2.2 Statements and circuits associated with PC
2.3 Statements and circuits associated with DR
2.4 Statements and circuits associated with AC
2.5 Statements and circuits associated with IR
2.6 Statements and circuits associated with TR
2.7 Statements and circuits associated with OUTR
2.8 Statements and circuits associated with INPR
2.9 Statements and circuits associated with SC
3. 단일 플립플롭에 대한 제어
3.1 Statements and circuits associated with I
3.2 Statements and circuits associated with S
3.3 Statements and circuits associated with E
3.4 Statements and circuits associated with R
3.5 Statements and circuits associated with IEN
3.6 Statements and circuits associated with FGI
3.7 Statements and circuits associated with FGO
4. 메모리에 대한 제어
5 공통 버스에 대한 제어
6. 누산기 논리의 설계
본문내용
1. 컴퓨터에 대한 제어 함수와 마이크로 연산
Fetch R’T0: AR PC
R’T1: IR M[AR] , PC PC+1
Decode R’T2: D0,,,,,,,,D7 Decode IR(12-14) AR IR(0-11) , I IR(15)
Indirect D7’IT3: AR M[AR]
InterruptT0’T1’T2’(IEN)(FGI+FGO) : R 1
RT0 : AR 0 , TR PC
RT1 : M[AR] TR , PC 0
RT2 : PC PC + 1 , IEN 0 , R 0 , SC 0
Memory-reference:
AND D0T4 : DR M[AR]
D0T5 : AC AC Ù DR , SC 0
ADD D1T4 : DR M[AR]
D1T5 : AC AC + DR , E Cout , SC 0
LDA D2T4 : DR M[AR]
D2T5 : AC DR , SC 0
STA D3T4 : M[AR] AC , SC 0
BUN D4T4 : PC AR , SC 0
BSA D5T4 : M[AR] PC , AR AR + 1
D5T5 : PC AR , SC 0
ISZ D6T4 : DR M[AR]
D6T5 : DR DR + 1
D6T6 : M[AR] DR , if(DR=0) then (PCPC+1) , SC0
Register-reference: D7I’T3 = r (common to all register-reference instructions) IR(i) = Bi ( i = 0,1,2,3,,,,,,11) r : SC 0
CLA rB11 : AC 0
CLE rB10 : E 0
CMA rB9 : AC AC
CME rB8 : E E
CIR rB7 : AC shr AC , AC(15) E , E AC(0)
CIL rB6 : AC shl AC , AC(0) E , E AC(15)
INC rB5 : AC AC + 1
SPA rB4 : If(AC(15) = 0) then (PC PC + 1 )
SNA rB3 : If(AC(15) = 1) then (PC PC +1 )
SZA rB2 : If(AC = 0) then (PC PC + 1 )
SZE rB1 : If(E = 0) then (PC PC +1 )
HLT rB0 : S 0
Input-outputD7IT3 = p (common to all input-output instructions)IR(i) = Bi(i = 6,7,8,9,10,11)p : SC 0
INP pB11 : AC(0-7) INPR , FGI 0
OUT pB10 : OUTR AC(0-7) , FGI 0
SKI pB9 : If (FGI = 1) then (PC PC + 1)
SKO pB8 : If (FGO = 1) then (PC PC + 1)
ION pB7 : IEN 1
IOF pB6 : IEN 0
Fetch R’T0: AR PC
R’T1: IR M[AR] , PC PC+1
Decode R’T2: D0,,,,,,,,D7 Decode IR(12-14) AR IR(0-11) , I IR(15)
Indirect D7’IT3: AR M[AR]
InterruptT0’T1’T2’(IEN)(FGI+FGO) : R 1
RT0 : AR 0 , TR PC
RT1 : M[AR] TR , PC 0
RT2 : PC PC + 1 , IEN 0 , R 0 , SC 0
Memory-reference:
AND D0T4 : DR M[AR]
D0T5 : AC AC Ù DR , SC 0
ADD D1T4 : DR M[AR]
D1T5 : AC AC + DR , E Cout , SC 0
LDA D2T4 : DR M[AR]
D2T5 : AC DR , SC 0
STA D3T4 : M[AR] AC , SC 0
BUN D4T4 : PC AR , SC 0
BSA D5T4 : M[AR] PC , AR AR + 1
D5T5 : PC AR , SC 0
ISZ D6T4 : DR M[AR]
D6T5 : DR DR + 1
D6T6 : M[AR] DR , if(DR=0) then (PCPC+1) , SC0
Register-reference: D7I’T3 = r (common to all register-reference instructions) IR(i) = Bi ( i = 0,1,2,3,,,,,,11) r : SC 0
CLA rB11 : AC 0
CLE rB10 : E 0
CMA rB9 : AC AC
CME rB8 : E E
CIR rB7 : AC shr AC , AC(15) E , E AC(0)
CIL rB6 : AC shl AC , AC(0) E , E AC(15)
INC rB5 : AC AC + 1
SPA rB4 : If(AC(15) = 0) then (PC PC + 1 )
SNA rB3 : If(AC(15) = 1) then (PC PC +1 )
SZA rB2 : If(AC = 0) then (PC PC + 1 )
SZE rB1 : If(E = 0) then (PC PC +1 )
HLT rB0 : S 0
Input-outputD7IT3 = p (common to all input-output instructions)IR(i) = Bi(i = 6,7,8,9,10,11)p : SC 0
INP pB11 : AC(0-7) INPR , FGI 0
OUT pB10 : OUTR AC(0-7) , FGI 0
SKI pB9 : If (FGI = 1) then (PC PC + 1)
SKO pB8 : If (FGO = 1) then (PC PC + 1)
ION pB7 : IEN 1
IOF pB6 : IEN 0
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