디지털 시계의 VHDL 소스

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디지털 시계의 VHDL 소스에 대한 보고서 자료입니다.

목차

디지털 시계의 VHDL 소스코드
◈ TOP
◈ clock_div
◈ clock1_div
◈ debounce
◈ MODE_GEN
◈ TIME
◈ TIMER
◈ SELECTOR
◈ int2seg2
◈ cnt_onetosix

본문내용

'0'&MIN_AL;
OUT_S <= "1111111";
when "01" =>--시간 알람설정
OUT_H <= "00" & HUR_AL;
OUT_M <= "1111111";
OUT_S <= "1111111";
when "10" => --분 알람설정
OUT_H <= "1111111";
OUT_M <= '0'&MIN_AL;
OUT_S <= "1111111";
when others =>
OUT_H <= "00" & HUR_AL;
OUT_M <= "1111111";
OUT_S <= '0'&MIN_AL;
end case;
end if;
end if;
end process SELECTION;
ALARM_SET : process (INCREASE, MODE1, MODE2, HUR_AL, MIN_AL, HOUR, MIN)
begin
if (INCREASE'event and INCREASE = '1') then
if (MODE1 = "10")then
if (MODE2 = "01") then
if (HUR_AL = "10111") then
HUR_AL <= "00000";
else HUR_AL <= HUR_AL + 1;
end if;
elsif (MODE2 = "10") then
if (MIN_AL = "111011") then
MIN_AL <= "000000";
else MIN_AL <= MIN_AL + 1;
end if;
else NULL;
end if;
end if;
end if;
if((HOUR = HUR_AL) and (MIN=MIN_AL)) then
ALARM <= '1';
else ALARM <= '0';
end if;
end process ALARM_SET;
end A_SELECTOR;
◈ int2seg2
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity int2seg2 is
port(reset : in std_logic;
int_value : in std_logic_vector (6 downto 0);
seg_10 : out std_logic_vector(6 downto 0);
seg_01 : out std_logic_vector(6 downto 0));
end int2seg2;
architecture design of int2seg2 is
component int2seg1 is
port (int : in std_logic_vector (6 downto 0);
seg : out std_logic_vector(6 downto 0));
end component;
signal dec_10 : std_logic_vector (6 downto 0);
signal dec_01 : std_logic_vector (6 downto 0);
begin
separate_int : process(reset, int_value)
begin
if(reset='0')then dec_10<="0000000"; dec_01<="0000000";
elsif(int_value >="1011010") then dec_10<="0001001";
dec_01 <=int_value-"1010010";
elsif(int_value >="1010000") then dec_10<="0001000";
dec_01 <=int_value-"1010000";
elsif(int_value >="1000110") then dec_10<="0000111";
dec_01 <=int_value-"1000110";
elsif(int_value >="0111100") then dec_10<="0000110";
dec_01 <=int_value-"1010010";
elsif(int_value >="0110010") then dec_10<="0000101";
dec_01 <=int_value-"0110010";
elsif(int_value >="0101000") then dec_10<="0000100";
dec_01 <=int_value-"0101000";
elsif(int_value >="0011110") then dec_10<="0000011";
dec_01 <=int_value-"0011110";
elsif(int_value >="0010100") then dec_10<="0000010";
dec_01 <=int_value-"0010100";
elsif(int_value >="0001010") then dec_10<="0000001";
dec_01 <=int_value-"0001010";
else dec_10 <= "0000000";
dec_01 <= int_value;
end if;
end process separate_int;
seg_10_ten : int2seg1 port map (int => dec_10, seg => seg_10);
seg_01_one : int2seg1 port map (int => dec_01, seg => seg_01);
end design;
◈ cnt_onetosix
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt_onetosix is
port( diclock : in std_logic;
reset : in std_logic;
value : out integer range 1 to 6);
end cnt_onetosix;
architecture beh of cnt_onetosix is
signal tmp_value : integer range 1 to 6;
begin
process(diclock, reset, tmp_value)
begin
if(reset = '0' ) then tmp_value <=1;
elsif (diclock'event and diclock='1')then
if(tmp_value = 6)then
tmp_value <= 1;
else
tmp_value<=tmp_value+1;
end if;
end if;
end process;
value<=tmp_value;
end beh;

키워드

디지털시계,   VHDL,   시계,   FPGA,   ISE