디지털시계 설계

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디지털시계 설계에 대한 보고서 자료입니다.

목차

설계 프로젝트 Ⅰ


1. 카운터 설계

2. 분주기 설계

3. 시계 및 시 조정 회로 설계와 동작원리

4. STOP WATCH 설계 및 동작원리

5. 세그먼트표시기

6. 코드분석

본문내용

C)
0:
AP=am;
1:
AP=pm;
endcase
if(Clk_N==10)
begin
sec=sec+1;
Clk_N=0;
end
if(sec==6\'b111100)
begin
sec=6\'b000000;
min=min+1;
end
if(min==6\'b111100)
begin
min=6\'b000000;
hour=hour+1;
if((hour == 4\'b1100) && (min==6\'b000000)&&
(sec==6\'b000000))
AP_C=~AP_C;
end
if(hour==4\'b1101)
hour=4\'b0001;
if(Stop_S==1)
Clk_N=Clk_N-1;
//Clock end
//dual clock
if(save_S==1)
begin
s_t=sec;
m_t=min;
h_t=hour;
AP_t=AP;
end
if(dual_S==1)
begin
sec=s_d;
min=m_d;
hour=hr_d;
AP=A_d;
end
if(return_S==1)
begin
sec=s_t;
min=m_t;
hour=h_t;
AP=AP_t;
end
//dual clock end
//Stop Watch
if(Start_S==1)
begin
if(Clk_N==1)
begin
sec=sec+1;
Clk_N=0;
end
if(sec==6\'b001010)
begin
sec=6\'b000000;
min=min+1;
end
if(min==6\'b111100)
begin
min=6\'b000000;
hour=hour+1;
end
end
//Stop Watch end
end
endmodule
module sec_gen(clk, sec);
input clk;
output sec;
reg sec;
reg [19:0] count;
always@ (posedge clk)
begin
sec=0;
count = count+1;
if(count==90000)
begin
sec=~sec;
count=0;
end
end
endmodule
module hour_p(hour_input, hour_out1, hour_out2);
parameter zero =7\'b0111111;
parameter one =7\'b0000110;
parameter two =7\'b1011011;
parameter three=7\'b1001111;
parameter four =7\'b1100110;
parameter five =7\'b1101101;
parameter six =7\'b1111101;
parameter seven=7\'b0100111;
parameter eight=7\'b1111111;
parameter nine =7\'b1101111;
input [3:0] hour_input;
output [6:0] hour_out1, hour_out2;
reg [6:0] hour_out1, hour_out2;
always@(hour_input or hour_out1 or hour_out2)
begin
case(hour_input)
4\'b0000:
begin
hour_out1=zero;
hour_out2=zero;
end
4\'b0001:
begin
hour_out1=zero;
hour_out2=one;
end
4\'b0010:
begin
hour_out1=zero;
hour_out2=two;
end
4\'b0011:
begin
hour_out1=zero;
hour_out2=three;
end
4\'b0100:
begin
hour_out1=zero;
hour_out2=four;
end
4\'b0101:
begin
hour_out1=zero;
hour_out2=five;
end
4\'b0110:
begin
hour_out1=zero;
hour_out2=six;
end
4\'b0111:
begin
hour_out1=zero;
hour_out2=seven;
end
4\'b1000:
begin
hour_out1=zero;
hour_out2=eight;
end
4\'b1001:
begin
hour_out1=zero;
hour_out2=nine;
end
4\'b1010:
begin
hour_out1=one;
hour_out2=zero;
end
4\'b1011:
begin
hour_out1=one;
hour_out2=one;
end
4\'b1100:
begin
hour_out1=one;
hour_out2=two;
end
endcase
end
endmodule
module dual(clk, sec_d, min_d,hour_d,AP_d);
parameter am =7\'b1110111;
parameter pm =7\'b1110011;
//Clock input
input clk;
output [5:0] sec_d, min_d;
output [3:0] hour_d;
output [6:0] AP_d;
reg gen_sec_d;
reg [3:0] Clk_N_d;
reg AP_C_d;
reg [6:0] AP_d;
reg [3:0] hour_d;
reg [5:0] min_d;
reg [5:0] sec_d;
sec_gen SG(clk, gen_sec_d);
//Initial Value
initial
begin
AP_d = am;
sec_d =6\'b000000;
min_d =6\'b000000;
hour_d=4\'b1100;
end
//always start
always@(posedge gen_sec_d)
begin
Clk_N_d=Clk_N_d+1;
//Clock
case(AP_C_d)
0:
AP_d=am;
1:
AP_d=pm;
endcase
if(Clk_N_d==10)
begin
sec_d=sec_d+1;
Clk_N_d=0;
end
if(sec_d==6\'b111100)
begin
sec_d=6\'b000000;
min_d=min_d+1;
end
if(min_d==6\'b111100)
begin
min_d=6\'b000000;
hour_d=hour_d+1;
if((hour_d == 4\'b1100) && (min_d==6\'b000000)&&
(sec_d==6\'b000000))
AP_C_d=~AP_C_d;
end
if(hour_d==4\'b1101)
hour_d=4\'b0001;
//Clock end
end
endmodule

키워드

디지털시계,   설계,   디지털