verilog 시계 [디지털 논리 회로]

목차

모듈 및 시뮬레이션

1. 기본 시계 제작 (0.1초~1분단위, 스탑워치)
㉮기본 시간 모듈
㉯스탑워치 모듈
㉰메인 모듈

2. hour 단위 구현을 위한 testbench & module
㉮분단위 test module
㉯시간단위 test module
㉰test main module

본문내용

:0] min_a;
reg [5:0] min_b;
reg [4:0] min_a;
initial
begin
min_a = 0;
min_b = 0;
end
always @(posedge c1k_c or posedge reset)
begin
if(reset)
begin
min_b<=4'd0;
min_a<=3'd0;
end
else if (c1k_c)
begin
if(comma_a==4'd9 & sec_b==4'd9 & sec_a==3'd5)
begin
if(min_b==4'd9)
begin
min_b<=4'd0;
if(min_a==3'd5)
min_a<=3'd0;
else
min_a<=min_a + 1'b1;
end
else
min_b<=min_b + 1'b1;
end
else begin
min_a<=min_a;
min_b<=min_b;
end
end
else begin
min_a<=min_a;
min_b<=min_b;
end
end
endmodule
㉯시간단위 test module
`timescale 1ns/100ps
module hour
(c1k,reset,comma_a,sec_b,sec_a,min_b,min_a,hour_b,hour_a,night_a,c1k_c);
input c1k,reset;
input [5:0] comma_a, sec_b, min_b;
input [4:0] sec_a, min_a;
input c1k_c;
output [5:0] hour_b;
output [2:0] hour_a;
output [3:0] night_a;
reg [5:0] hour_b;
reg [2:0] hour_a;
reg [3:0] night_a;
initial
begin
hour_a = 0;
hour_b = 0;
night_a = 4'hA;
end
always @(posedge c1k_c or posedge reset)
begin
if(reset) begin
hour_b<=4'd0;
hour_a<=2'd0;
end
else if (c1k_c) begin
if(comma_a==4'd9 & sec_b==4'd9 & sec_a==4'd5 & min_b==4'd9 & min_a==3'd5)
begin
if(hour_b==4'd9)
begin
hour_b<=4'd0;
hour_a<=hour_a + 1'b1;
end
else if(comma_a==4'd9 & sec_b==4'd9 & sec_a==4'd5 & min_b==4'd9 & min_a==3'd5 & hour_b==4'd1 & hour_a==3'd1)
begin
night_a<=4'hb;
hour_b<=hour_b+1'b1;
end
else if(comma_a==4'd9 & sec_b==4'd9 & sec_a==4'd5 & min_b==4'd9 & min_a==3'd5 & hour_b==4'd3 & hour_a==3'd2)
begin
hour_b<=4'd0;
hour_a<=3'd0;
night_a<=4'ha;
end
else
hour_b<=hour_b+1'b1;
end
else begin
hour_a<=hour_a;
hour_b<=hour_b;
end
end
else begin
hour_a<=hour_a;
hour_b<=hour_b;
end
end
endmodule
㉰test main module
`timescale 100ns/1ns
module
tb_min_hour(c1k,reset,comma_a,night_a,sec_b,sec_a,c1k_b,c1k_c,min_b,min_a,hour_b,hour_a);
input [5:0] min_b, hour_b;
input [4:0] min_a;
input [2:0] hour_a;
input [3:0] night_a;
output c1k,reset;
output [5:0] comma_a, sec_b;
output [4:0] sec_a;
output c1k_c;
output [17:0] c1k_b;
reg [5:0] comma_a, sec_b;
reg [4:0] sec_a;
reg c1k_c;
reg [17:0] c1k_b;
reg c1k,reset;
initial
begin
c1k=1;
reset=0;
c1k_b = -1;
c1k_c = 0;
comma_a=0;
sec_a = 0;
sec_b = 0;
end
always
begin
c1k = #5 ~c1k;
end
always @ (posedge c1k or posedge reset)
begin
if (c1k_b == 18'd9)
begin
c1k_b <= 0;
c1k_c <= 1;
end
else
begin
c1k_b <= c1k_b + 1;
c1k_c = 0;
end
end
always @ (posedge c1k_c or posedge reset)
begin
if(reset)
begin
sec_b <= 0;
comma_a <= 0;
end
else if(comma_a == 9)
begin
comma_a <= 0;
sec_b <= sec_b + 1;
end
else
begin
comma_a <= comma_a + 1;
end
end
always @(posedge c1k_c or posedge reset)
begin
if (reset) begin
sec_a<=3'd0;
sec_b<=4'd0;
end
else if (c1k_c) begin
if(comma_a==4'd9) begin
if(sec_b==4'd9) begin
sec_b<=4'd0;
if(sec_a==4'd5)
sec_a<=4'd0;
else
sec_a<=sec_a+1;
end
else
sec_b<=sec_b+1'b1;
end
else begin
sec_a<=sec_a;
sec_b<=sec_b;
end
end
else begin
sec_a<=sec_a;
sec_b<=sec_b;
end
end
min mi(c1k,reset,comma_a,sec_b,sec_a,min_b,min_a,c1k_c);
hour ho(c1k,reset,comma_a,sec_b,sec_a,min_b,min_a,hour_b,hour_a,night_a,c1k_c);
endmodule

키워드

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