비교기설계

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비교기설계에 대한 보고서 자료입니다.

본문내용

GB<= \'1\';
ALB <= \'0\';
else
EQ <= \'0\';
AGB<= \'0\';
ALB <= \'1\';
end if;
end process;
end behave_bit_4;
4Bit Test Bench
Library IEEE;
use IEEE.std_logic_1164.all;
entity tb_bit_4 is
end tb_bit_4;
architecture tb_behave of tb_bit_4 is
signal A, B : std_logic_vector(3 downto 0);
signal EQ, AGB, ALB : std_logic;
component bit_4
port(
A, B : in std_logic_vector(3 downto 0);
EQ, AGB, ALB : out std_logic
);
end component;
begin
u0: bit_4
port map(A, B, EQ, AGB, ALB);
A <= \"0000\", \"1111\" after 300 ns, \"0000\" after 500 ns;
B <= \"0000\", \"0000\" after 300 ns, \"1111\" after 500 ns;
end tb_behave;
4Bit 파형

키워드

비교기설계,   공학,   설계