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본문내용
_logic;
Q : out std_logic
);
end component;
signal D_in, c, Q_out : std_logic_vector (3 downto 0)
begin
C(0) <= EN;
C(1) <= C(0) and Q_out(0);
C(2) <= C(1) and Q_out(1);
C(3) <= C(2) and Q_out(2);
CO <= C(3) and Q_out(3);
D_in(0) <= C(0) xor Q_out(0);
D_in(1) <= C(1) xor Q_out(1);
D_in(2) <= C(2) xor Q_out(2);
D_in(3) <= C(3) xor Q_out(3);
bit0 : diff
port map(Clock, Reset, D_in(0), Q_out(0));
bit1 : diff
port map(Clock, Reset, D_in(1), Q_out(1));
bit2 : diff
port map(Clock, Reset, D_in(2), Q_out(2));
bit3 : diff
port map(Clock, Reset, D_in(3), Q_out(3));
Q <= Q_out;
end counter_4_bit_arch;
Q : out std_logic
);
end component;
signal D_in, c, Q_out : std_logic_vector (3 downto 0)
begin
C(0) <= EN;
C(1) <= C(0) and Q_out(0);
C(2) <= C(1) and Q_out(1);
C(3) <= C(2) and Q_out(2);
CO <= C(3) and Q_out(3);
D_in(0) <= C(0) xor Q_out(0);
D_in(1) <= C(1) xor Q_out(1);
D_in(2) <= C(2) xor Q_out(2);
D_in(3) <= C(3) xor Q_out(3);
bit0 : diff
port map(Clock, Reset, D_in(0), Q_out(0));
bit1 : diff
port map(Clock, Reset, D_in(1), Q_out(1));
bit2 : diff
port map(Clock, Reset, D_in(2), Q_out(2));
bit3 : diff
port map(Clock, Reset, D_in(3), Q_out(3));
Q <= Q_out;
end counter_4_bit_arch;
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