디지털 시스템 설계

목차

• 반가산기

• 전가산기

본문내용

_1164.all;
entity scdrum3 is
port(A, B : in std_logic_vector(3 downto 0);
S : out std_logic_vector(3 downto 0);
Ci : in std_logic;
Bo : out std_logic);
end scdrum3;
architecture ksc of scdrum3 is
signal borrow0, borrow1, borrow2,
borrow3: std_logic;
component scdrum2
port(A,B,Ci : in std_logic;
S, Bo : out std_logic);
end component;
begin
f0 : scdrum2 port map(A=>A(0), B=>B(0),
Ci=>borrow0, S=>Sd(0), Bo =>borrow1);
f1 : scdrum2 port map(A=>A(1), B=>B(1),
Ci=>borrow1, S=>d(1), Bo =>borrow2);
f2 : scdrum2 port map(A=>A(2), B=>B(2),
Ci=>borrow2, S=>S(2), Bo =>borrow3);
f3 : scdrum2 port map(A=>A(3), B=>B(3),
Ci=>borrow3, S=>S(3), Bo=>Bo);
borrow0<=Ci ;
end ksc;
BCD 가산기
<진리표> <논리표>
BCD 가산기 시물레이터 결과 값

Library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scdrum4 is
port ( s,w : in std_logic_vector(3 downto 0);
c_in : in std_logic;
y :buffer std_logic_vector(3 downto 0);
s_out : out std_logic_vector(3 downto 0);
c_out : out std_logic);
end scdrum4;
architecture ksc of scdrum4 is
begin
process(s,w,c_in)
begin
y <= s+w;
if (c_in='0') then
if (y="1010") then
s_out <= "0000";
c_out <= '1';
elsif (y="1011") then
s_out <= "0001";
c_out <= '1';
elsif (y="1100") then
s_out <= "0010";
c_out <= '1';
elsif (y="1101") then
s_out <= "0011";
c_out <= '1';
elsif (y="1110") then
s_out <= "0100";
c_out <= '1';
elsif (y="1111") then
s_out <= "0101";
c_out <= '1';
else
s_out <= y;
c_out <= '0';
end if;
end if;
end process;
end ksc;

키워드

반가산기 ,   전가산기,   BCD 가산기,   4비트 감산기