디지털 논리회로 111 detection(감지)

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디지털 논리회로 111 detection(감지)에 대한 보고서 자료입니다.

목차

mealy code
counter code
simulation code

본문내용

aly;
architecture Behavioral of counter_mealy is
type st_mealy is( a, b, c, d, e, f, g, h, i, j ,k ,l ,m ,n, o, p);
signal state : st_mealy;
signal s_input : std_logic;
begin
process(m_reset,m_clk)
begin
if m_reset = '1' then
s_input <= '0';
elsif rising_edge(m_clk) then
s_input <= m_input;
end if;
end process;
process(m_reset,m_clk)
begin
if m_reset = '1' then
state <= a;
elsif rising_edge(m_clk) then
case state is
when a =>
if s_input = '1' then
state <= b;
m_output <= "0001";
else
state <= a;
m_output <= "0000";
end if;
when b =>
if s_input = '1' then
state <= c;
m_output <= "0010";
else
state <= b;
end if;
when c =>
if s_input = '1' then
state <= d;
m_output <= "0011";
else
state <= c;
end if;
when d =>
if s_input = '1' then
state <= e;
m_output <= "0100";
else
state <= d;
end if;
when e =>
if s_input = '1' then
state <= f;
m_output <= "0101";
else
state <= e;
end if;
when f =>
if s_input = '1' then
state <= g;
m_output <= "0110";
else
state <= f;
end if;
when g =>
if s_input = '1' then
state <= h;
m_output <= "0111";
else
state <= g;
end if;
when h =>
if s_input = '1' then
state <= i;
m_output <= "1000";
else
state <= h;
end if;
when i =>
if s_input = '1' then
state <= j;
m_output <= "1001";
else
state <= i;
end if;
when j =>
if s_input = '1' then
state <= k;
m_output <= "1010";
else
state <= j;
end if;
when k =>
if s_input = '1' then
state <= l;
m_output <= "1011";
else
state <= k;
end if;
when l =>
if s_input = '1' then
state <= m;
m_output <= "1100";
else
state <= l;
end if;
when m =>
if s_input = '1' then
state <= n;
m_output <= "1101";
else
state <= m;
end if;
when n =>
if s_input = '1' then
state <= o;
m_output <= "1110";
else
state <= n;
end if;
when o =>
if s_input = '1' then
state <= p;
m_output <= "1111";
else
state <= o;
end if;
when p =>
if s_input = '1' then
state <= p;
m_output <= "1111";
else
state <= o;
m_output <= "1111";
end if;
end case;
end if;
end process;
end Behavioral;
●Simulation result
m_s (s신호)가 1이 나온 뒤 count가 0000 이 된다.
count가 0000이 된 후 입력 값에 따라 다시 111 detection을 함을 보인다.
output은 delay 가 돼서 나온다.
counter 가 1111이 된 후 더 이상 count 하지 않음을 보인다.
1111 다음에 m_s (s) 가 1이 들어와서 counter가 0000으로 된다.
즉, 동작을 반복함을 보인다.

키워드

detect,   디지털,   mealy,   moore,   디지털회로설계,   VHDL