목차
4단원 연습문제입니다.
2번 9번 16번 23번 30번 37번 44번 51번
2번 9번 16번 23번 30번 37번 44번 51번
본문내용
s that are a good test for the priority function it performs.
library IEEE;
use IEEE.std_logc_1164.all;
entity priority is
port(D: in std_logic_vector(3 downto 0);
A : out std_logic_vector(1 downto 0);
V : out std_logic);
end priority;
architecture structural of priority is
begin
V <= '0' when D="0000" else '1';
A <= "11" when D(3) = '1' else
"10" when D(2) = '1' else
"01" when D(1) = '1' else
"00" when D(0) = '1' else "00";
end structural;
4. 51 Using Figure 4-33 as a framework, write a structural Verilog description of the circuit in Figure 4-40. Replace x, y and Z with input [2:0] x. Compile
module circuit(X, F);
input[2:0] X;
output F;
wire[0:4] T:
nand
g0(T[0],X[0],X[1]),
g1(T[1],X[0],T[0]),
g2(T[2],X[1],T[0]),
g3(T[3],X[2],T[1],T[2]),
g4(T[4],X[2],T[2]),
g5(F,T[3],T[4]);
endmodule
library IEEE;
use IEEE.std_logc_1164.all;
entity priority is
port(D: in std_logic_vector(3 downto 0);
A : out std_logic_vector(1 downto 0);
V : out std_logic);
end priority;
architecture structural of priority is
begin
V <= '0' when D="0000" else '1';
A <= "11" when D(3) = '1' else
"10" when D(2) = '1' else
"01" when D(1) = '1' else
"00" when D(0) = '1' else "00";
end structural;
4. 51 Using Figure 4-33 as a framework, write a structural Verilog description of the circuit in Figure 4-40. Replace x, y and Z with input [2:0] x. Compile
module circuit(X, F);
input[2:0] X;
output F;
wire[0:4] T:
nand
g0(T[0],X[0],X[1]),
g1(T[1],X[0],T[0]),
g2(T[2],X[1],T[0]),
g3(T[3],X[2],T[1],T[2]),
g4(T[4],X[2],T[2]),
g5(F,T[3],T[4]);
endmodule
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