[VHDL] Digital stop watch[디지털 스톱 워치]설계 소스 - 키트와 쿼터스를 이용

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[VHDL] Digital stop watch[디지털 스톱 워치]설계 소스 - 키트와 쿼터스를 이용에 대한 보고서 자료입니다.

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본문내용

<='0';
when "100" => muxout <= minlow; dp <='1';
when others=> muxout <= minhigh; dp <='0';
end case;
end process;
process(cnt)
begin
case cnt is
when "000" => p_out <= "011111";
when "001" => p_out <= "101111";
when "010" => p_out <= "110111";
when "011" => p_out <= "111011";
when "100" => p_out <= "111101";
when "101" => p_out <= "111110";
when others => p_out <= "111111";
end case;
end process;
process(muxout)
variable seg_decode : std_logic_vector(6 downto 0);
begin
case muxout is
when "0000" => seg_decode := "1111110";
when "0001" => seg_decode := "0110000";
when "0010" => seg_decode := "1101101";
when "0011" => seg_decode := "1111001";
when "0100" => seg_decode := "0110011";
when "0101" => seg_decode := "1011011";
when "0110" => seg_decode := "1011111";
when "0111" => seg_decode := "1110000";
when "1000" => seg_decode := "1111111";
when "1001" => seg_decode := "1110011";
when others => seg_decode := "0000000";
end case;
if dp = '1' then
seg_out <= seg_decode;
else
seg_out <= seg_decode;
end if;
end process;
end hb;
컴포넌트 사례화문 분석
architecture hb of stopwatch is
component hz-- 1kHz로부터 1/100초 주파수를 생성
port(clk, nclr : in std_logic;
hz100 : out std_logic);
end component;
component key
port(start_stop : in std_logic;
clk, nclr : in std_logic;
enp : out std_logic);
end component;
component timecontrol
port(clk, nclr : in std_logic;
enp : in std_logic;
sslow : out std_logic_vector(3 downto 0);
sshigh : out std_logic_vector(3 downto 0);
seclow : out std_logic_vector(3 downto 0);
sechigh : out std_logic_vector(3 downto 0);
minlow : out std_logic_vector(3 downto 0);
minhigh : out std_logic_vector(3 downto 0));
end component;
component output
port(clk, nclr : in std_logic;
sslow : in std_logic_vector(3 downto 0);
sshigh : in std_logic_vector(3 downto 0);
seclow : in std_logic_vector(3 downto 0);
sechigh : in std_logic_vector(3 downto 0);
minlow : in std_logic_vector(3 downto 0);
minhigh : in std_logic_vector(3 downto 0);
p_out : out std_logic_vector(5 downto 0);
seg_out : out std_logic_vector(6 downto 0));
end component;
signal nclr : std_logic;
signal hz100 : std_logic;
signal enp : std_logic;
signal sslow : std_logic_vector(3 downto 0);
signal sshigh : std_logic_vector(3 downto 0);
signal seclow : std_logic_vector(3 downto 0);
signal sechigh : std_logic_vector(3 downto 0);
signal minlow : std_logic_vector(3 downto 0);
signal minhigh : std_logic_vector(3 downto 0);
signal p_out : std_logic_vector(5 downto 0);
signal seg_out : std_logic_vector(6 downto 0);
begin
nclr <= not reset;
u1 : hz port map(clk,nclr,hz100);
u2 : key port map(start_stop,clk,nclr,enp);
u3 : timecontrol port map(hz100, nclr,enp,sslow,sshigh,seclow,sechigh,minlow,minhigh);
u4 : output port map(clk,nclr,sslow,sshigh,seclow,sechigh,minlow,minhigh,p_out,seg_out);
p0 <= p_out(5);
p1 <= p_out(4);
p2 <= p_out(3);
p3 <= p_out(2);
p4 <= p_out(1);
p5 <= p_out(0);
a <= seg_out(6);
b <= seg_out(5);
c <= seg_out(4);
d <= seg_out(3);
e <= seg_out(2);
f <= seg_out(1);
g <= seg_out(0);
end hb;

키워드

VHDL,   디지털 스톱 워치,   설계 소스 ,   키트와 쿼터스를 이용,   수행 내용,   컴포넌트 사례화문 분석,   [VHDL] Digital stop watch[디지털 스톱 워치] 설계