mux_decoder_encoder_비교기_곱셈기_VHDL

목차

Decoder(4bit BCD)

Multiplexer(8비트)

Encoder(4bit)

Comparator(4bit)

Multiplier(2bit)

본문내용

pe ab_value is integer range 0 to 2**ab_width-1;
end my_package;
library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;
entity comparator is
port ( a,b : in std_logic_vector(3 downto 0);
aleeb, abiggerb, aequalb : out std_logic);
end comparator;
architecture arc of comparator is
begin
process(a, b)
begin
if(a(3)>b(3))then
abiggerb<='1';
aleeb<='0';
aequalb<='0';
elsif(a(3) aleeb<='1';
abiggerb<='0';
aequalb<='0';
else
if(a(2)>b(2))then
abiggerb<='1';
aleeb<='0';
aequalb<='0';
elsif(a(2) aleeb<='1';
abiggerb<='0';
aequalb<='0';
else
if(a(1)>b(1))then
abiggerb<='1';
aleeb<='0';
aequalb<='0';
elsif(a(1) aleeb<='1';
abiggerb<='0';
aequalb<='0';
else
if(a(0)>b(0))then
abiggerb<='1';
aleeb<='0';
aequalb<='0';
elsif(a(0) aleeb<='1';
abiggerb<='0';
aequalb<='0';
else
aequalb<='1';
aleeb<='0';
abiggerb<='0';
end if;
end if;
end if;
end if;
end process;
end arc;
Multiplier(2bit)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multi is
port( a : in unsigned (1 downto 0);
b : in unsigned (1 downto 0);
result : out unsigned (3 downto 0));
end entity;
architecture arc of multi is
begin
result <= a * b;
end arc;

키워드

VHDL,   mux,   decoder,   encoder,   비교기,   곱셈기