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library ieee;
use ieee.std_logic_1164.all;
entity control is port(
clk : in std_logic;
st_op: in std_logic;
sw1 : in bit;
sw2 : in bit;
segcontrol : out std_logic_vector(3 downto 0);
segment : out std_logic_vector(6 downto 0));
end control;
archit
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dge clk) begin
q[3]<=e;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule
================================================
================================================
module shift4(clk, e, q);
input clk, e;
output [3:0] q;
reg [3:0] q;
always @(posedge clk) begin
q[0]<=q[1];
q[1]
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efinitions
m_clk_process :process
begin
m_clk <= \'0\';
wait for m_clk_period/2;
m_clk <= \'1\';
wait for m_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
m_reset <= \'0\';
wait for 50 ns;
startsig <= \'1\';
wait f
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efinitions
m_clk_process :process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
m_reset <= '0';
wait for 50 ns;
startsig <= '1';
wait for 50 ns
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========================
clk-q delay(ps)
215.816
215.184
222.305
232.065
244.905
clk-q_bar delay
167.045
166.520
173.879
183.094
197.563
두 번째는 첫 번째와 반대로 입력 값이 Vin=0 일 경우이다. 즉 클럭은 일정하게 두고서 클럭의 라이징 에지에 Vin의 0값 변화점이 점점 접근
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door_lock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity door_lock is
port(
clk : in std_logic;
sw1,sw2 : in std_logic;
key1 : in std_logic;
clear : in std_logic;
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